#ifndef F28P65X_PIEVECT_H
#define F28P65X_PIEVECT_H

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------
// PIE Interrupt Vector Table Definition:
// Create a user type called PINT (pointer to interrupt):

typedef void (*PINT)(void);

// Define Vector Table:
struct PIE_VECT_TABLE
{
    // Lower PIE Group 0
    PINT BUSERROR0_INT;     // 0.1 - bus error 0
    PINT BUSERROR1_INT;     // 0.2 - bus error 1
    PINT BUSERROR2_INT;     // 0.3 - bus error 2
    PINT BUSERROR3_INT;     // 0.4 - bus error 3
    PINT ILLEGALINST_INT;   // 0.5 - exception illegal instruction
    PINT OVERFLOW_INT;      // 0.6 - exception overflow
    PINT ILLEGALADDR_INT;   // 0.7 - exception illegal address
    PINT EXCEPTION3_INT;    // 0.8 - exception 3
    PINT UNAVOIDEDPIC0_INT; // 0.9 - unavoided pic 0
    PINT PIE0_RESERVED_INT; // 0.10
    PINT PIE1_RESERVED_INT; // 0.11
    PINT PIE2_RESERVED_INT; // 0.12
    PINT PIE3_RESERVED_INT; // 0.13
    PINT PIE4_RESERVED_INT; // 0.14
    PINT PIE5_RESERVED_INT; // 0.15
    PINT PIE6_RESERVED_INT; // 0.16

    // Lower PIE Group 1
    PINT RTOS_INT;      // 1.1 - RTOS Interrupt
    PINT ADCA1_INT;     // 1.2 - ADCA Interrupt 1
    PINT ADCB1_INT;     // 1.3 - ADCB Interrupt 1
    PINT ADCC1_INT;     // 1.4 - ADCC Interrupt 1
    PINT XINT1_INT;     // 1.5 - XINT1 Interrupt
    PINT XINT2_INT;     // 1.6 - XINT2 Interrupt
    PINT TIMER0_INT;    // 1.7 - Timer 0 Interrupt
    PINT WAKE_INT;      // 1.8 - Halt Wakeup/Watchdog Interrupt
    PINT ADCF1_INT;     // 1.9 - ADCF Interrupt 1
    PINT ADCF2_INT;     // 1.10 - ADCF Interrupt 2
    PINT SYS_ERR_INT;   // 1.11 - SYS ERROR Interrupt
    PINT BGCRC_INT;     // 1.11 - BGCRC Interrupt
    PINT ECATSYNC0_INT; // 1.11 - ETHCAT SYNC 0 Interrupt
    PINT ECAT_INT;      // 1.12 - ETHCAT Interrupt
    PINT CIPC0_INT;     // 1.13 - CIPC 0 Interrupt
    PINT CIPC1_INT;     // 1.14 - CIPC 1 Interrupt
    PINT CIPC2_INT;     // 1.15 - CIPC 2 Interrupt
    PINT CIPC3_INT;     // 1.16 - CIPC 3 Interrupt

    // Lower PIE Group 2
    PINT EPWM1_TZ_INT;  // 2.1 - ePWM1 Trip Zone Interrupt
    PINT EPWM2_TZ_INT;  // 2.2 - ePWM2 Trip Zone Interrupt
    PINT EPWM3_TZ_INT;  // 2.3 - ePWM3 Trip Zone Interrupt
    PINT EPWM4_TZ_INT;  // 2.4 - ePWM4 Trip Zone Interrupt
    PINT EPWM5_TZ_INT;  // 2.5 - ePWM5 Trip Zone Interrupt
    PINT EPWM6_TZ_INT;  // 2.6 - ePWM6 Trip Zone Interrupt
    PINT EPWM7_TZ_INT;  // 2.7 - ePWM7 Trip Zone Interrupt
    PINT EPWM8_TZ_INT;  // 2.8 - ePWM8 Trip Zone Interrupt
    PINT EPWM9_TZ_INT;  // 2.9 - ePWM9 Trip Zone Interrupt
    PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt
    PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt
    PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt
    PINT EPWM13_TZ_INT; // 2.13 - ePWM13 Trip Zone Interrupt
    PINT EPWM14_TZ_INT; // 2.14 - ePWM14 Trip Zone Interrupt
    PINT EPWM15_TZ_INT; // 2.15 - ePWM15 Trip Zone Interrupt
    PINT EPWM16_TZ_INT; // 2.16 - ePWM16 Trip Zone Interrupt

    // Lower PIE Group 3
    PINT EPWM1_INT;  // 3.1 - ePWM1 Interrupt
    PINT EPWM2_INT;  // 3.2 - ePWM2 Interrupt
    PINT EPWM3_INT;  // 3.3 - ePWM3 Interrupt
    PINT EPWM4_INT;  // 3.4 - ePWM4 Interrupt
    PINT EPWM5_INT;  // 3.5 - ePWM5 Interrupt
    PINT EPWM6_INT;  // 3.6 - ePWM6 Interrupt
    PINT EPWM7_INT;  // 3.7 - ePWM7 Interrupt
    PINT EPWM8_INT;  // 3.8 - ePWM8 Interrupt
    PINT EPWM9_INT;  // 3.9 - ePWM9 Interrupt
    PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt
    PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt
    PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt
    PINT EPWM13_INT; // 3.13 - ePWM13 Interrupt
    PINT EPWM14_INT; // 3.14 - ePWM14 Interrupt
    PINT EPWM15_INT; // 3.15 - ePWM15 Interrupt
    PINT EPWM16_INT; // 3.16 - ePWM16 Interrupt

    // Lower PIE Group 4
    PINT ECAP1_INT;   // 4.1 - eCAP1 Interrupt
    PINT ECAP2_INT;   // 4.2 - eCAP2 Interrupt
    PINT ECAP3_INT;   // 4.3 - eCAP3 Interrupt
    PINT ECAP4_INT;   // 4.4 - eCAP4 Interrupt
    PINT ECAP5_INT;   // 4.5 - eCAP5 Interrupt
    PINT ECAP6_INT;   // 4.6 - eCAP6 Interrupt
    PINT ECAP7_INT;   // 4.7 - eCAP7 Interrupt
    PINT ADCD1_INT;   // 4.8 - ADCD1 Interrupt
    PINT FSITXA1_INT; // 4.9 - FSITXA Interrupt 1
    PINT FSITXA2_INT; // 4.10 - FSITXA Interrupt 2
    PINT FSITXB1_INT; // 4.11 - FSITXB Interrupt 1
    PINT FSITXB2_INT; // 4.12 - FSITXB Interrupt 2
    PINT FSIRXA1_INT; // 4.13 - FSIRXA Interrupt 1
    PINT FSIRXA2_INT; // 4.14 - FSIRXA Interrupt 2
    PINT FSIRXB1_INT; // 4.15 - FSIRXB Interrupt 1
    PINT FSIRXB2_INT; // 4.16 - FSIRXB Interrupt 2

    // Lower PIE Group 5
    PINT EQEP1_INT;     // 5.1 - eQEP1 Interrupt
    PINT EQEP2_INT;     // 5.2 - eQEP2 Interrupt
    PINT EQEP3_INT;     // 5.3 - eQEP3 Interrupt
    PINT EQEP4_INT;     // 5.4 - eQEP4 Interrupt
    PINT CLB1_INT;      // 5.5 - CLB1 Interrupt
    PINT CLB2_INT;      // 5.6 - CLB2 Interrupt
    PINT CLB3_INT;      // 5.7 - CLB4 Interrupt
    PINT CLB4_INT;      // 5.8 - CLB8 Interrupt
    PINT SDFM1_INT;     // 5.9 - SDFM1 Interrupt
    PINT SDFM2_INT;     // 5.10 - SDFM2 Interrupt
    PINT ECATSRT_INT;   // 5.11 - ETHCAT RST Interrupt
    PINT ECATSYNC1_INT; // 5.12 - ETHCAT SYNC1 Interrupt
    PINT SDFM1DR1_INT;  // 5.13 - SDFM1DR1 Interrupt
    PINT SDFM1DR2_INT;  // 5.14 - SDFM1DR2 Interrupt
    PINT SDFM1DR3_INT;  // 5.15 - SDFM1DR3 Interrupt
    PINT SDFM1DR4_INT;  // 5.16 - SDFM1DR4 Interrupt

    // Lower PIE Group 6
    PINT SPIA_RX_INT;  // 6.1 - SPIA Receive Interrupt
    PINT SPIA_TX_INT;  // 6.2 - SPIA Transmit Interrupt
    PINT SPIB_RX_INT;  // 6.3 - SPIB Receive Interrupt
    PINT SPIB_TX_INT;  // 6.4 - SPIB Transmit Interrupt
    PINT LINA_INT;     // 6.5 - LINA Interrupt
    PINT ADCE1_INT;    // 6.6 - ADCE1 Interrupt
    PINT LINB_INT;     // 6.7 - LINB Interrupt
    PINT ADCE2_INT;    // 6.8 - ADCE2 Interrupt
    PINT SPIC_RX_INT;  // 6.9 - SPIC Receive Interrupt
    PINT SPIC_TX_INT;  // 6.10 - SPIC Transmit Interrupt
    PINT SPID_RX_INT;  // 6.11 - SPID Receive Interrupt
    PINT SPID_TX_INT;  // 6.12 - SPID Transmit Interrupt
    PINT SDFM2DR1_INT; // 6.13 - SDFM2DR1 Interrupt
    PINT SDFM2DR2_INT; // 6.14 - SDFM2DR2 Interrupt
    PINT SDFM2DR3_INT; // 6.15 - SDFM2DR3 Interrupt
    PINT SDFM2DR4_INT; // 6.16 - SDFM2DR4 Interrupt

    // Lower PIE Group 7
    PINT DMA_CH1_INT;  // 7.1 - DMA Channel 1 Interrupt
    PINT DMA_CH2_INT;  // 7.2 - DMA Channel 2 Interrupt
    PINT DMA_CH3_INT;  // 7.3 - DMA Channel 3 Interrupt
    PINT DMA_CH4_INT;  // 7.4 - DMA Channel 4 Interrupt
    PINT DMA_CH5_INT;  // 7.5 - DMA Channel 5 Interrupt
    PINT DMA_CH6_INT;  // 7.6 - DMA Channel 6 Interrupt
    PINT EQEP5_INT;    // 7.7 - EQEP5 Interrupt
    PINT EQEP6_INT;    // 7.8 - EQEP6 Interrupt
    PINT FSIRXC1_INT;  // 7.9 - FSIRXC Interrupt 1
    PINT FSIRXC2_INT;  // 7.10 - FSIRXC Interrupt 2
    PINT FSIRXD1_INT;  // 7.11 - FSIRXD Interrupt 1
    PINT FSIRXD2_INT;  // 7.12 - FSIRXD Interrupt 2
    PINT SDFM3DR1_INT; // 7.13 - SDFM3DR1 Interrupt
    PINT SDFM3DR2_INT; // 7.14 - SDFM3DR2 Interrupt
    PINT SDFM3DR3_INT; // 7.15 - SDFM3DR3 Interrupt
    PINT SDFM3DR4_INT; // 7.16 - SDFM3DR4 Interrupt

    // Lower PIE Group 8
    PINT I2CA_INT;      // 8.1 - I2CA Interrupt
    PINT I2CA_FIFO_INT; // 8.2 - I2CA  FIFO Interrupt
    PINT I2CB_INT;      // 8.3 - I2CB Interrupt
    PINT I2CB_FIFO_INT; // 8.4 - I2CB  FIFO Interrupt
    PINT UARTA_INT;     // 8.5 - UARTA Interrupt
    PINT UARTB_INT;     // 8.6 - UARTB Interrupt
    PINT EPWM17_TZ_INT; // 8.7 - EPWM17 TZ Interrupt
    PINT EPWM18_TZ_INT; // 8.8 - EPWM18 TZ Interrupt
    PINT ADCG4_INT;     // 8.9 - ADCG4 Interrupt
    PINT ADCF4_INT;     // 8.10 - ADCF4 Interrupt
    PINT SDFM3_INT;     // 8.11 - SDFM3 Interrupt
    PINT SDFM4_INT;     // 8.12 - SDFM4 Interrupt
    PINT CLB5_INT;      // 8.13 - CLB5 Interrupt
    PINT CLB6_INT;      // 8.14 - CLB6 Interrupt
    PINT ADCE3_INT;     // 8.15 - ADCE3 Interrupt
    PINT ADCE4_INT;     // 8.16 - ADCE4 Interrupt

    // Lower PIE Group 9
    PINT SCIA_RX_INT;         // 9.1 - SCIA RX Interrupt
    PINT SCIA_TX_INT;         // 9.2 - SCIA TX Interrupt
    PINT SCIB_RX_INT;         // 9.3 - SCIB RX Interrupt
    PINT SCIB_TX_INT;         // 9.4 - SCIB TX Interrupt
    PINT CANA_INT;            // 9.5 - CANA Interrupt
    PINT ADCG_EVT_INT;        // 9.6 - ADCG EVT Interrupt
    PINT EPWM17_INT;          // 9.7 - EPWM17 Interrupt
    PINT EPWM18_INT;          // 9.8 - EPWM18 Interrupt
    PINT MCANA_INT;           // 9.9 - MCANA Interrupt
    PINT ADCG1_INT;           // 9.10 - ADCG1 Interrupt
    PINT ADCG2_INT;           // 9.11 - ADCG2 Interrupt
    PINT ADCG3_INT;           // 9.12 - ADCG3 Interrupt
    PINT PMBUSA_INT;          // 9.13 - PMBUSA Interrupt
    PINT AES_SINTREQUEST_INT; // 9.14 - AES_SINTREQUEST Interrupt
    PINT ADCE_EVT_INT;        // 9.15 - ADCE_EVT Interrupt
    PINT EMIF_INT;            // 9.16 - EMIF Interrupt

    // Lower PIE Group 10
    PINT ADCA_EVT_INT;    // 10.1 - ADCA Event Interrupt
    PINT ADCA2_INT;       // 10.2 - ADCA Interrupt 2
    PINT ADCA3_INT;       // 10.3 - ADCA Interrupt 3
    PINT ADCA4_INT;       // 10.4 - ADCA Interrupt 4
    PINT ADCB_EVT_INT;    // 10.5 - ADCB Event Interrupt
    PINT ADCB2_INT;       // 10.6 - ADCB Interrupt 2
    PINT ADCB3_INT;       // 10.7 - ADCB Interrupt 3
    PINT ADCB4_INT;       // 10.8 - ADCB Interrupt 4
    PINT ADCC_EVT_INT;    // 10.9 - ADCC Event Interrupt
    PINT ADCC2_INT;       // 10.10 - ADCC Interrupt 2
    PINT ADCC3_INT;       // 10.11 - ADCC Interrupt 3
    PINT ADCC4_INT;       // 10.12 - ADCC Interrupt 4
    PINT ADCD2_INT;       // 10.13 - ADCD Interrupt 2
    PINT ADCD3_INT;       // 10.14 - ADCD Interrupt 3
    PINT ADCD4_INT;       // 10.15 - ADCD Interrupt 4
    PINT ADCCHECKINT_INT; // 10.16 - ADC CHECK Interrupt

    // Lower PIE Group 11
    PINT CLA1_1_INT;   // 11.1 - CLA1 interrupts
    PINT CLA1_2_INT;   // 11.2 - CLA2 interrupts
    PINT CLA1_3_INT;   // 11.3 - CLA3 interrupts
    PINT CLA1_4_INT;   // 11.4 - CLA4 interrupts
    PINT CLA1_5_INT;   // 11.5 - CLA5 interrupts
    PINT CLA1_6_INT;   // 11.6 - CLA6 interrupts
    PINT CLA1_7_INT;   // 11.7 - CLA7 interrupts
    PINT CLA1_8_INT;   // 11.8 - CLA8 interrupts
    PINT MCANB_INT;    // 11.9 - MCANB interrupts
    PINT ADCD_EVT_INT; // 11.10 - ADCD EVT interrupts
    PINT ADH3_INT;     // 11.10 - ADCH interrupts 3
    PINT ADH4_INT;     // 11.11 - ADCH interrupts 4
    PINT SDFM4DR1_INT; // 11.13 - SDFM4DR1 Interrupt
    PINT SDFM4DR2_INT; // 11.14 - SDFM4DR2 Interrupt
    PINT SDFM4DR3_INT; // 11.15 - SDFM4DR3 Interrupt
    PINT SDFM4DR4_INT; // 11.16 - SDFM4DR4 Interrupt

    // Lower PIE Group 12
    PINT XINT3_INT;         // 12.1 - XINT3 Interrupt
    PINT XINT4_INT;         // 12.2 - XINT4 Interrupt
    PINT XINT5_INT;         // 12.3 - XINT5 Interrupt
    PINT CLA1_CICP0_INT;    // 12.4 - CLA1_CIPC0 Interrupt
    PINT CLA1_CICP1_INT;    // 12.5 - CLA1_CIPC1 Interrupt
    PINT CLA1_CICP2_INT;    // 12.6 - CLA1_CIPC2 Interrupt
    PINT CLA1_CICP3_INT;    // 12.7 - CLA1_CIPC3 Interrupt
    PINT ADCH_EVT_INT;      // 12.8 - ADCH EVT Interrupt
    PINT ADCF3_INT;         // 12.9 - ADCF Interrupt
    PINT ECAP6_2_INT;       // 12.10 - HR ECAP6 Interrupt
    PINT ECAP7_2_INT;       // 12.11 - HR ECAP7 Interrupt
    PINT ADCH1_INT;         // 12.12 - ADCH Interrupt 1
    PINT ADCH2_INT;         // 12.13 - ADCH Interrupt 2
    PINT ADCF_EVT_INT;      // 12.14 - ADCF EVT Interrupt
    PINT CLA_OVERFLOW_INT;  // 12.14 - CLA_OVERFLOW Interrupt
    PINT CLA_UNDERFLOW_INT; // 12.15 - CLA_UNDERFLOW Interrupt

    PINT TIMER1_INT;             // 13.1 - CPU Timer 1 Interrupt
    PINT PIE92_RESERVED_INT[15]; // 13.2 ~ 13.16

    PINT TIMER2_INT;             // 14.1 - CPU Timer 2 Interrupt
    PINT PIE93_RESERVED_INT[15]; // 14.2 ~ 14.16

    PINT NMI_INT;                // 15.1 - Non-Maskable Interrupt
    PINT PIE94_RESERVED_INT[15]; // 15.2 ~ 15.16
};

//---------------------------------------------------------------------------
// PieVect External References & Function Declarations:
//

extern volatile struct PIE_VECT_TABLE PieVectTable;

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif // end of F28P65X_PIEVECT_H definition
//===========================================================================
// End of file.
//===========================================================================
